Oscillator Tolerance: While

the auto baud rate detection

mechanism has a wide

tolerance for oscillator error,

the QT’s oscillator should still

from the recommended value.

Beyond a 20% error,

communications at either the

lower or upper stated limits

could fail. The oscillator

frequency can be checked

with an oscilloscope by

probing the pulse width on

the SNS lines; these should ideally be 2.15µs in width each

at the beginning of a burst with the recommended

spread-spectrum circuit, or 2µs wide if no spread-spectrum

circuit is used.

Host Request Byte: The host requests the key state from

the QT1101 by sending an ASCII "P" character (ASCII

decimal code 80, hex 0x50) over the 1W line. The character

is formatted according to conventional RS-232:

8 data bits

no parity

1 stop bit

baud rate: 8,000 - 38,400

Figure 2.2 shows the bit pattern of the host request byte

(‘P’). The first bit labeled ‘S’ is the start bit, the last ‘S’ is the

stop bit. This bit pattern should never be changed. The

QT1101 will respond at the same baud rate as the received

‘P’ character.

After sending the ‘P’ character the host must immediately

float the 1W signal to prevent a drive conflict between the

host and the QT1101 (see Figure 2.1). The delay from the

received stop bit to the QT1101 driving the 1W pin is in the

range 1-3 bit periods, so the host should float the pin within

one bit period to prevent a drive conflict.

Data Reply: Before sending a reply, the QT1101 returns the

/CHANGE signal to its inactive (float-high) state.

The QT1101 then replies by sending two eight-bit characters

to the host over the 1W line using the same baud rate as the

request. With no keys pressed, both repl y bytes are ASCII

‘@’ (0x40) characters; any keys that are pressed at the time

of the reply result in their associated bits being set in the

reply. Figure 2.3 shows the reply bytes when keys 0, 2 and 7

are pressed - 0x45, 0x42, and the associations between

keys and bits in the reply.

The QT1101 floats the 1W pin again after establishing the

level of the stop bit.

2.11.2 LP Mode Effects on 1W

The use of low power (LP) mode

presents some additional 1W timing

requirements. In LP mode (Section

2.5), the QT1101 will only respond to

a request from the host when it is

making one of its infrequent checks

for a key press. Hence, in that

condition most requests from the host

to the QT1101 will be ignored, since

the QT1101 will be sleeping and

unresponsive. However, if either

/CHANGE or DETECT are active the

QT1101 will be at full speed, and hence will always respond

to ‘P’ requests.

Note that when sleeping in LP mode, there are by definition

no keys active, so there should not be a reason for the host

to send the ‘P’ query command in the first place.

Three strategies are available to the host to ensure that LP

mode operates correctly:

# /CHANGE used. The host monitors /CHANGE, and only

sends a ‘P’ request when it is low. The part is awake by

definition when /CHANGE is low. If /CHANGE is high,

key states are known to be unchanged since the last

reply received from the QT1101, and so additional ‘P’

requests are not needed. Before triggering LP mode the

host should wait for /CHANGE to go high after all keys

have become inactive.

# DETECT used. The host monitors DETECT, and if it is

active (i.e. the part is awake) it polls the device regularly

to obtain key status. When DETECT is inactive (the part

may be sleeping) no requests are sent because it is

known that no keys are active. Before triggering LP

mode the host should wait for DETECT to become

inactive, and then send one additional 'P' request to

ensure /CHANGE is also made inactive.

# Neither /CHANGE nor DETECT used. The host polls

the device regularly to obtain key status, with a timeout

in operation when awaiting the reply to each ‘P’ request.

Not receiving a reply within the timeout period only

occurs when the part is sleeping, and hence when no

keys are active. Before triggering LP mode the host

should wait for all keys to become inactive and then

send an additional 'P' request to the QT1101 to ensure

/CHANGE is also inactive.

2.11.3 2W Operation

1W operation, as described above, requires that the host

float the 1W line while awaiting a reply from the QT1101; this

is not always possible.

8

QT1101 R4.06/0806

Figure 2.3 UART Response Pattern on 1W Pin

(Shown with keys 0, 2 and 7 detecting)

* Fixed bit values

U - Unused bits

S 0 1 23456 7

S 0 12345 67 S

01 2345 **

6 789 U U **

Serial bits

Associated key #

1W

(from QT1101)

S

floating

floating

floating

Figure 2.4 2W Operation

1W

(from QT1101)

/CHANGE

RX

(from host)

key state

change

request

from host

(1 byte)

driven reply

from QT1101

(2 bytes)

floating

floating

floating

floating

1 ~ 3 bit periods