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74HC4024 Datasheet(PDF) 3 Page - Nexperia B.V. All rights reserved |
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74HC4024 Datasheet(HTML) 3 Page - Nexperia B.V. All rights reserved |
3 / 13 page ![]() Nexperia 74HC4024 7-stage binary ripple counter 6.2. Pin description Table 2. Pin description Symbol Pin Description CP 1 clock input (HIGH-to-LOW, edge-triggered) MR 2 master reset input (active HIGH) Q6, Q5, Q4, Q3, Q2, Q2, Q1, Q0 3, 4, 5, 6, 9, 11, 12 parallel output GND 7 ground (0 V) n.c. 8, 10, 13 not connected VCC 14 positive supply voltage 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; ↓ = HIGH-to-LOW clock transition. Input Output MR CP Qn H X L ↑ no change L ↓ count 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage -0.5 +7 V IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA IO output current VO = -0.5 V to VCC + 0.5 V - ±25 mA ICC supply current - 50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation [1] - 500 mW [1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. 74HC4024 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 10 — 23 November 2018 3 / 13 |
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