Nexperia

74HC4024

7-stage binary ripple counter

11.1. Waveforms and test circuit

MR input

CP input

Q0 or Qn

output

tW

tPHL

1/fmax

trec

VM

VM

001aab910

tPLH

tW

tTLH

tTHL

tPHL

VM

90 %

90 %

10 %

10 %

Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the

master reset to clock (CP) recovery time.

VM = 0.5 x VCC.

Fig. 6. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output

transition times and the maximum clock frequency

001aah768

tW

tW

tr

tr

tf

VM

VI

negative

pulse

GND

VI

positive

pulse

GND

10 %

90 %

90 %

10 %

VM

VM

VM

tf

VCC

DUT

RT

VI

VO

CL

G

Test data is given in Table 8.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

Fig. 7. Test circuit for measuring switching times

Table 8. Test data

Supply

Input

Load

VCC

VI

tr, tf

CL

2.0 V

VCC

6 ns

50 pF

4.5 V

VCC

6 ns

50 pF

6.0 V

VCC

6 ns

50 pF

5.0 V

VCC

6 ns

15 pF

74HC4024

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2018. All rights reserved

Product data sheet

Rev. 10 — 23 November 2018

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