HY5PS1G821M datasheet(5/79 Pages) HYNIX

Part #	HY5PS1G821M

Description	1Gb DDR2 SDRAM(DDP)

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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5 / 79 page

Rev. 0.2 / Oct. 2005

5

1HY5PS12421(L)M

HY5PS12821(L)M

1.1 Device Features & Ordering Information

1.1.1 Key Features

• Dual Die Package( 512Mb DDR2 * 2)

• VDD, VDDQ=1.8V +/- 0.1V

• All inputs and outputs are compatible with SSTL_18 interface

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)

• Differential Data Strobe (DQS, DQS)

• Data outputs on DQS, DQS edges when read (edged DQ)

• Data inputs on DQS centers when write(centered DQ)

• On chip DLL align DQ, DQS and DQS transition with CK transition

• DM mask write data-in at the both rising and falling edges of the data strobe

• All addresses and control inputs except data, data strobes and data masks latched on the rising

edges of the clock

• Programmable CAS latency 3, 4, 5 supported

• Programmable additive latency 0, 1, 2, 3, 4 supported

• Programmable burst length 4/8 with both nibble sequential and interleave mode

• Internal 4bank operations with single pulsed RAS

• Auto refresh and self refresh supported

• tRAS lockout supported

• 8K refresh cycles /64ms

• JEDEC standard 60ball FBGA(x4/x8)

• Full strength driver option controlled by EMRS

• On Die Termination supported

• Off Chip Driver Impedance Adjustment supported

• Read Data Strobe supported (x8 only)

• Self-Refresh High Temperature Entry

Ordering Information

Part No.

Configuration Package

HY5PS1G421(L)M-X*

256Mx4

63Ball

HY5PS1G821(L)M-X*

128Mx8

Operating Frequency

Grade

tCK(ns)

CL

tRCD

tRP

Unit

-E3

53

3

Clk

-C4

3.75

4

Clk

Note: -X* is the speed bin, refer to the Operation

Frequency table for complete Part No.

1. Description

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HY5PS1G821M Datasheet(PDF) 5 Page - Hynix Semiconductor

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