 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ST72F324J2T3 Datasheet(PDF) 143 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST72F324J2T3 Datasheet(HTML) 143 Page - STMicroelectronics |
|
|
143 / 163 page  ST72324 143/163 ADC CHARACTERISTICS (Cont’d) Figure 83. RAIN max. vs fADC with CAIN=0pF 1) Figure 84. Recommended CAIN & RAIN values. 2) Figure 85. Typical A/D Converter Application Notes: 1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca- pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 2. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and decreased to allow the use of a larger serial resistor (RAIN). 0 5 10 15 20 25 30 35 40 45 010 30 70 CPARASITIC (pF) 2 MHz 1 MHz 0.1 1 10 100 1000 0.01 0.1 1 10 fAIN(KHz) Cain 10 nF Cain 22 nF Cain 47 nF AINx ST72XXX VDD IL ±1 µA VT 0.6V VT 0.6V CADC 12pF VAIN RAIN 10-Bit A/D Conversion 2k Ω(max) CAIN 1 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
