ST72F262G2B6 datasheet(129/172 Pages) STMICROELECTRONICS

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OPERATING CONDITIONS (Cont’d)

13.3.2 Operating Conditions with Low Voltage Detector (LVD)

TA = -40 to +85°C unless otherwise specified

Notes:

1. Data based on characterization results, not tested in production.

2. When VtPOR is faster than 100 µs/V, the Reset signal is released after a delay of max. 42µs after VDD crosses the

VIT+(LVD) threshold.

3. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is

recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 91 on page

151 and note 6.

Figure 65. LVD Startup Behaviour

Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state.

However, in some devices, the reset signal may be undefined until VDD is approximately 2V. As a conse-

quence, the I/Os may toggle when VDD is below this voltage.

Because Flash write access is impossible below this voltage, the Flash memory contents will not be cor-

rupted.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIT+(LVD)

Reset release threshold

(VDD rise)

High Threshold

Med. Threshold

Low Threshold

4.0 1)

3.55 1)

2.95 1)

4.2

3.75

3.15

4.5

4.0

3.35

VIT-(LVD)

Reset generation threshold

(VDD fall)

High Threshold

Med. Threshold

Low Threshold

3.75

3.3

2.75

4.0

3.55

3.0

4.251)

3.751)

3.151)

Vhys(LVD)

LVD voltage threshold hysteresis

VIT+(LVD)-VIT-(LVD)

200

VtPOR

VDD rise time rate

1)2)3)

Flash

µs/V

20ms/V

ROM

µs/V

∞

tg(VDD)

Filtered glitch delay on VDD

Not detected by the LVD

VIT+

LVD RESET

V D

Reset state

in this area

not defined

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