ST72F262G2B6 datasheet(144/172 Pages) STMICROELECTRONICS

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ST72260Gx, ST72262Gx, ST72264Gx

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13.8 I/O PORT PIN CHARACTERISTICS

13.8.1 General Characteristics

TA = -40 to +85°C unless otherwise specified

Notes:

1. Data based on characterization results, not tested in production.

2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be

respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD

while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the

corresponding VIN maximum must always be respected.

Caution: Negative current injection not allowed on Flash device pins PB0 and PB1.

3. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see Figure 76). Data

based on design simulation and/or technology characteristics, not tested in production.

4. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-

scribed in Figure 77).

5. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

Figure 76. Two typical Applications with unused I/O Pin configured as input

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage1)

Vss - 0.3

0.3xVDD

VIH

Input high level voltage1)

0.7xVDD

VDD + 0.3

Vhys

Schmitt trigger voltage hysteresis 1)

400

IINJ(PIN)

Injected current on Flash device

pins PB0 and PB1

Injected Current on other I/O pins

VDD=5V

±4

ΣI

INJ(PIN)

2) Total injected current (sum of all I/O

and control pins)

±25

Input leakage current

VSS≤VIN≤VDD

±1

µA

Static current consumption

Floating input mode3)

400

RPU

Weak pull-up equivalent resistor 4)

VIN=VSS

VDD=5V

250

Ω

VDD=3V

1701)

190

2301)

CIO

I/O pin capacitance

tf(IO)out

Output high to low level fall time 1)

CL=50pF

Between 10% and 90%

tr(IO)out

Output low to high level rise time 1)

tw(IT)in

External interrupt pulse time5)

1tCPU

10k

Ω

UNUSED I/O PORT

ST7XXX

10k

Ω

UNUSED I/O PORT

ST7XXX

VDD

Note: I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of greater EMC

robustness and lower cost.

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