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WM8985GEFL/R Datasheet(PDF) 102 Page - Wolfson Microelectronics plc |
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WM8985GEFL/R Datasheet(HTML) 102 Page - Wolfson Microelectronics plc |
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102 / 118 page  WM8985 Pre-Production w PP, Rev 3.5, March 2007 102 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 39 (27h) 8:0 PLLK[8:0] 011101001 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 8:4 00000 Reserved. Initialise to 0 41 (29h) 3:0 DEPTH3D 0000 Stereo depth 0000: 0% (minimum 3D effect) 0001: 6.67% .... 1110: 93.3% 1111: 100% (maximum 3D effect) 3D Stereo Enhancement 8:6 OUT4_2ADCVOL 000 Controls the OUT4 to ADC input boost stage: 000 = Path disabled (disconnected) 001 = -12dB gain 010 = -9dB gain 011 = -6dB gain 100 = -3dB gain 101 = +0dB gain 110 = +3dB gain 111 = +6dB gain 5 OUT4_2LNR 0 OUT4 to L or R ADC input 0 = Right ADC input 1 = Left ADC input 4:0 0 0000 Reserved. Initialise to 0 42 (2Ah) 2 POBCTRL 0 VMID independent current bias control 0 = Disable VMID independent current bias 1 = Enable VMID independent current bias Analogue Outputs 8 BYPL2RMIX 0 Left bypass path (from the Left channel input PGA stage) to right output mixer 0 = not selected 1 = selected Analogue Outputs 7 BYPR2LMIX 0 Right bypass path (from the right channel input PGA stage) to Left output mixer 0 = not selected 1 = selected Analogue Outputs 6 0 Reserved. Initialise to 0 5 MUTERPGA2INV 0 Mute input to INVROUT2 mixer Analogue Outputs 4 INVROUT2 0 Mute input to INVROUT2 mixer Analogue Outputs 3:1 BEEPVOL 000 AUXR input to ROUT2 inverter gain 000 = -15dB ... 111 = +6dB Analogue Outputs 43 (2Bh) 0 BEEPEN 0 0 = mute AUXR beep input 1 = enable AUXR beep input Analogue Outputs 8 MBVSEL 0 Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD Input Signal Path 7 0 Reserved. Initialise to 0 44 (2Ch) 6 R2_2INPPGA 0 Connect R2 pin to right channel input PGA positive terminal. 0=R2 not connected to input PGA 1=R2 connected to input PGA amplifier positive terminal (constant input impedance). Input Signal Path |
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