7

AT25010/020/040

0606M–SEEPR–06/03

is applied. All programming instructions must therefore be preceded by a Write Enable

instruction. The WP pin must be held high during a WREN instruction.

WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write

Disable instruction disables all programming modes. The WRDI instruction is indepen-

dent of the status of the WP pin.

READ STATUS REGISTER (RDSR): The Read Status Register instruction provides

access to the status register. The READY/BUSY and Write Enable status of the device

can be determined by the RDSR instruction. Similarly, the Block Write Protection bits

indicate the extent of protection employed. These bits are set by using the WRSR

instruction.

WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select

one of four levels of protection. The AT25010/020/040 is divided into four array seg-

ments. Top quarter (1/4), Top half (1/2), or all of the memory segments can be

protected. Any of the data within any selected segment will therefore be READ only. The

block write protection levels and corresponding status register control bits are shown in

Table 4.

The two bits, BP1 and BP0 are nonvolatile cells that have the same properties and func-

tions as the regular memory cells (e.g. WREN, t

Table 2. Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

X

X

X

X

BP1

BP0

WEN

RDY

Table 3. Read Status Register Bit Definition

Bit

Definition

Bit 0 (RDY)

Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the

write cycle is in progress.

Bit 1 (WEN)

Bit 1 = 0 indicates the device

the device is WRITE ENABLED.

Bit 2 (BP0)

See Table 4.

Bit 3 (BP1)

See Table 4.

Bits 4-7 are 0s when device is not in an internal write cycle.

Bits 0-7 are 1s during an internal write cycle.

Table 4. Block Write Protect Bits

Level

Status Register Bits

Array Addresses Protected

BP1

BP0

AT25010

AT25020

AT25040

0

0

0

NoneNoneNone

1 (1/4)

0

1

60-7F

C0-FF

180-1FF

2 (1/2)

1

0

40-7F

80-FF

100-1FF

3 (All)

1

1

00-7F

00-FF

000-1FF