Electronic Components Datasheet Search |
|
RTL8201CL-VD Datasheet(PDF) 10 Page - Realtek Semiconductor Corp. |
|
|
RTL8201CL-VD Datasheet(HTML) 10 Page - Realtek Semiconductor Corp. |
10 / 39 page RTL8201CL Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver 4 Track ID: JATR-1076-21 Rev. 1.24 5. Pin Descriptions LI: Latched Input during Power up or Reset O: Output I: Input IO: Bi-directional input and output P: Power 5.1. MII Interface Table 1. MII Interface Name Type Pin No. Description TXC O 7 Transmit Clock. This pin provides a continuous clock as a timing reference for TXD[3:0] and TXEN. TXEN I 2 Transmit Enable. The input signal indicates the presence of valid nibble data on TXD[3:0]. An internal weak pull low resistor prevents the bus floating. TXD[3:0] I 3, 4, 5, 6 Transmit Data. The MAC will source TXD[0..3] synchronous with TXC when TXEN is asserted. An internal weak pull high resistor prevents the bus floating. RXC O 16 Receive Clock. This pin provides a continuous clock reference for RXDV and RXD[0..3] signals. RXC is 25MHz in 100Mbps mode and 2.5Mhz in 10Mbps mode. COL LI/O 1 Collision Detect. COL is asserted high when a collision is detected on the media. During power on reset, this pin status is latched to determine at which LED mode to operate: 0: CL LED mode 1: BL LED mode An internal weak pull low resistor sets this to the default CL LED mode. It is possible to use an external 5.1KΩ pull high resistor to enable BL LED mode. CRS LI/O 23 Carrier Sense. This pin’s signal is asserted high if the media is not in Idle state. An internal weak pull low resistor sets this to normal operation mode. An external 5.1KΩ pull low resistor could be reserved to ensure operating at normal mode. RXDV O 22 Receive Data Valid. This pin’s signal is asserted high when received data is present on the RXD[3:0] lines. The signal is de-asserted at the end of the packet. The signal is valid on the rising edge of the RXC. RXD[3:0] O 18, 19, 20, 21 Receive Data. These are the four parallel receive data lines aligned on the nibble boundaries driven synchronously to the RXC for reception by the external physical unit (PHY). www.DataSheet4U.net |
Similar Part No. - RTL8201CL-VD |
|
Similar Description - RTL8201CL-VD |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |