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RTL8201CL-VD Datasheet(PDF) 11 Page - Realtek Semiconductor Corp. |
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RTL8201CL-VD Datasheet(HTML) 11 Page - Realtek Semiconductor Corp. |
11 / 39 page ![]() RTL8201CL Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver 5 Track ID: JATR-1076-21 Rev. 1.24 Name Type Pin No. Description RXER/ FXEN O/LI 24 Receive Error. If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or invalid symbol, this pin will go high. Fiber/UTP Enable. During power on reset, this pin status is latched to determine the media mode to operate in. 1: Fiber mode 0: UTP mode An internal weak pull low resistor sets this to the default of UTP mode. It is possible to use an external 5.1KΩ pull high resistor to enable fiber mode. After power on, the pin operates as the Receive Error pin. MDC I 25 Management Data Clock. This pin provides a clock synchronous to MDIO, which may be asynchronous to the transmit TXC and receive RXC clocks. The clock rate can be up to 2.5MHz. An internal weak pull high resistor prevents the bus floating. MDIO IO 26 Management Data Input/Output. This pin provides the bi-directional signal used to transfer management information. 5.2. SNI (Serial Network Interface) 10Mbps Only Table 2. SNI (Serial Network Interface) 10Mbps Only Name Type Pin No. Description COL O 1 Collision Detect. RXD0 O 21 Received Serial Data. CRS O 23 Carrier Sense. RXC O 16 Receive Clock. Resolved from received data. TXD0 I 6 Transmit Serial Data. TXC O 7 Transmit Clock. Generated by PHY. TXEN I 2 Transmit Enable. For MAC to indicate transmit operation. 5.3. Clock Interface Table 3. Clock Interface Name Type Pin No. Description X2 O 47 25MHz Crystal Output. This pin provides the 25MHz crystal output. It must be left open when an external 25MHz oscillator drives X1. X1 I 46 25MHz Crystal Input. This pin provides the 25MHz crystal input. If a 25MHz oscillator is used, connect X1 to the oscillator’s output (see 8.3 Crystal Characteristics, page 30, for clock source specifications. www.DataSheet4U.net |
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