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RTL8201CL-VD Datasheet(PDF) 25 Page - Realtek Semiconductor Corp. |
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RTL8201CL-VD Datasheet(HTML) 25 Page - Realtek Semiconductor Corp. |
25 / 39 page ![]() RTL8201CL Datasheet Single-Chip/Port 10/100 Fast Ethernet PHYceiver 19 Track ID: JATR-1076-21 Rev. 1.24 7.5. LED and PHY Address Configuration In order to reduce the pin count on the RTL8201CL, the LED pins are duplexed with the PHY address pins. Because the PHYAD strap options share the LED output pins, the external combinations required for strapping and LED usage must be considered in order to avoid contention. Specifically, when the LED outputs are used to drive LEDs directly, the active state of each output driver is dependent on the logic level sampled by the corresponding PHYAD input upon power-up/reset. For example, as Figure 5 (left- side) shows, if a given PHYAD input is resistively pulled high then the corresponding output will be configured as an active low driver. On the right side, we can see that if a given PHYAD input is resistively pulled low then the corresponding output will be configured as an active high driver. The PHY address configuration pins should not be connected to GND or VCC directly, but must be pulled high or low through a resistor (ex 5.1KΩ). If no LED indications are needed, the components of the LED path (LED+510Ω) can be removed. PAD[0:4]/ LED[0:4] PAD[0:4]/ LED[0:4] VCC LED 510 ohm 5.1K ohm LED 5.1K ohm 510 ohm PHY Address[:] = Logical 1 PHY Address[:] = Logical 0 LED Indication = Active low LED Indication = Active High Figure 5. LED and PHY Address Configuration Table 27. LED Definitions LED LED Definitions LED0 Link LED1 Full Duplex LED2 [CL LED Mode]10-Activity LED3 [CL LED Mode]Fiber/100-Activity LED4 Collision www.DataSheet4U.net |
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