RTL8201CL-VD datasheet(27/39 Pages) REALTEK

Part #	RTL8201CL-VD

Description	SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER

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Manufacturer	REALTEK [Realtek Semiconductor Corp.]

Direct Link	https://www.realtek.com/en/

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RTL8201CL

Datasheet

Single-Chip/Port 10/100 Fast Ethernet PHYceiver

21

Track ID: JATR-1076-21 Rev. 1.24

The transmitter will first assert TXEN. Before transmitting the data pattern, it will send a /J/K/ symbol

(Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-Frame

delimiter. The 4B/5B and the scramble process can be bypassed via a PHY register setting (see Table 1,

page 4, Pin number 24). For better EMI performance, the seed of the scrambler is based on the PHY

address. In a hub/switch environment, each RTL8201CL will have different scrambler seeds and so

spread the output of the MLT-3 signals.

100Base-TX Receive Function

The received signal is compensated by the adaptive equalizer to make up for signal loss due to cable

attenuation and Inter Symbol Interference (ISI). Baseline Wander Correction monitors the process and

dynamically applies corrections to the process of signal equalization. The PLL then recovers the timing

information from the signals and from the receive clock. With this, the received signal is sampled to form

NRZI data. The next steps are the NRZI to NRZ process, unscrambling of the data, serial to parallel and

5B to 4B conversion, and passing of the 4B nibble to the MII interface.

7.8.2.

100Base-FX Fiber Mode Operation

The RTL8201CL can be configured as 100Base-FX via hardware configuration. The hardware

100Base-FX setting takes priority over NWay settings. A scrambler is not required in 100Base-FX.

100Base-FX Transmit Function

Di-bits of TXD are processed as 100Base-TX except without a scrambler before the NRZI stage. Instead

of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL

signals, which enter the fiber transceiver in differential-pairs form.

100Base-FX Receive Function

The signal is received through PECL receiver inputs from the fiber transceiver and directly passed to the

clock recovery circuit for data/clock recovery. The scrambler/de-scrambler is bypassed in 100Base-FX.

7.8.3.

10Base-T TX/RX

10Base-T Transmit Function

Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 2.5MHz (TXC) is first fed to a parallel-to-serial

converter, then the 10Mbps NRZ signal is sent to a Manchester encoder. The Manchester encoder

converts the 10Mbps NRZ data into a Manchester Encoded data stream for the TP transmitter and adds a

Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Finally, the encoded data

stream is shaped by a bandlimited filter embedded in the RTL8201CL and then transmitted.

10Base-T Receive Function

In 10Base-T receive mode, the Manchester decoder in the RTL8201CL converts the Manchester encoded

data stream into NRZ data by decoding the data and stripping off the SOI pulse. Then the serial NRZ data

stream is converted to a parallel 4-bit nibble signal (RXD[0:3]).

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RTL8201CL-VD Datasheet(PDF) 27 Page - Realtek Semiconductor Corp.

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