RTL8201CL

Datasheet

Single-Chip/Port 10/100 Fast Ethernet PHYceiver

22

Track ID: JATR-1076-21 Rev. 1.24

7.9. Repeater Mode Operation

Setting bit 15 of register 17 to 1, or pulling the RPTR pin high, sets the RTL8201CL into repeater mode.

In repeater mode, the RTL8201CL will assert CRS high only when receiving a packet. In NIC mode, the

RTL8201CL will assert CRS high both when transmitting and receiving packets. If using the

RTL8201CL in a NIC or switch application, set to the default mode. NIC/Switch mode is the default

setting and has the RPTR pin pulled low, or bit 15 of register 17 is set to 0.

7.10. Reset, and Transmit Bias

The RTL8201CL can be reset by pulling the RESETB pin low for about 10ms, then pulling the pin high.

It can also be reset by setting bit 15 of register 0 to 1, and then setting it back to 0. Reset will clear the

registers and re-initialize them. The media interface will disconnect and restart the auto-

negotiation/parallel detection process.

The RTSET pin must be pulled low by a 2KΩ resister with 1% accuracy to establish an accurate transmit

bias. This will affect the signal quality of the transmit waveform. Keep its circuitry away from other clock

traces and transmit/receive paths to avoid signal interference.

7.11. 3.3V Power Supply and Voltage Conversion Circuit

The RTL8201CL is fabricated in a 0.18

µm process. The core circuit needs to be powered by 1.8V,

however, the digital IO and DAC circuits need a 3.3V power supply. A regulator is embedded in the

RTL8201CL to convert 3.3V to 1.8V. As with many commercial voltage conversion devices, the 1.8V

output pin (PWFBOUT) of this circuit requires the use of an output capacitor (22uF tantalum capacitor)

as part of the device frequency compensation, and another small capacitor (0.1uF) for high frequency

noise de-coupling.

PWFBIN is fed with the 1.8V power from PWFBOUT through a ferrite bead as shown in the reference

design schematic document (available for download from www.realtek.com.tw).

Note: Do not supply 1.8V produced by any power device other than PWFBOUT and PWFBIN.

The analog and digital ground planes should be as large and intact as possible. If the ground plane is large

enough, the analog and digital grounds can be separated, which is the ideal configuration. However, if the

total ground plane is not sufficiently large, partition of the ground plane is not a good idea. In this case,

all the ground pins can be connected together to a larger single and intact ground plane.

7.12. Far End Fault Indication

The MII Reg.1.4 (Remote Fault) is the Far End Fault Indication (FEFI) bit when 100FX mode is enabled

and indicates when a FEFI has been detected. FEFI is an alternative in-band signaling method which is

composed of 84 consecutive ‘1’s followed by one ‘0’. When the RTL8201CL detects this pattern three

times, Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem. On

the other hand, if an incoming signal fails to cause a ‘Link OK’, the RTL8201CL will start sending this

pattern, which in turn causes the remote side to detect a Far End Fault. This means that the receive path

has a problem from the point of view of the RTL8201CL. The FEFI mechanism is used only in

100Base-FX mode.

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