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AM263P4 Datasheet(PDF) 128 Page - Texas Instruments |
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AM263P4 Datasheet(HTML) 128 Page - Texas Instruments |
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128 / 154 page  6.11.5.13.2 PRU-ICSS PRU Sigma Delta and Peripheral Interface 6.11.5.13.2.1 PRU-ICSS PRU Sigma Delta and Peripheral Interface Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input Slew Rate 1 3 V/ns OUTPUT CONDITIONS CL Output Load Capacitance 2 18 pF 6.11.5.13.2.2 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT PRSD1 tc(SD_CLK) Cycle time, SD_CLK 40 ns PRSD2L tw(SD_CLKL) Pulse duration, SD_CLK Low 20 ns PRSD2H tw(SD_CLKH) Pulse duration, SD_CLK High 20 ns PRSD3 tsu(SD_D-SDCLK) Setup time, SD_D valid before SD_CLK active edge 10 ns PRSD4 tsu(SDCLK-SD_D) Hold time, SD_D valid after SD_CLK active edge 5 ns SDx_CLK PRU_TIMING_07 PRSD2H PRSD2L PRSD4 PRSD3 SDx_D PRSD1 Figure 6-48. PRU-ICSS PRU SD_CLK Falling Active Edge SDx_CLK PRSD2L PRSD3 PRSD4 PRU_TIMING_08 SDx_D Figure 6-49. PRU-ICSS PRU SD_CLK Rising Active Edge 6.11.5.13.2.3 PRU-ICSS PRU Timing Requirements - Peripheral Interface Mode NO. PARAMETER DESCRIPTION MIN MAX UNIT PRPIF1 tw(PIF_DATA_INH) Pulse duration, PIF_DATA_IN High 2 + 0.475 × (4 × P(1)) ns PRPIF2 tw(PIF_DATA_INL) Pulse duration, PIF_DATA_IN Low 2 + 0.475 × (4 × P(1)) ns (1) P = 1x (or TX) clock period, defined by TX_DIV_FACTOR and TX_DIV_FACTOR_FRAC in the CFG_ED_P<n>_TXCFG register. TI Information - Selective Disclosure AM263P4, AM263P2, AM263P1, AM263P4-Q1, AM263P2-Q1, AM263P1-Q1 SPRSP81 – OCTOBER 2023 www.ti.com 128 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated |
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