ST92F124 datasheet(356/429 Pages) STMICROELECTRONICS

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CONTROLLER AREA NETWORK (bxCAN)

CONTROLLER AREA NETWORK (Cont’d)

Bit 2 = FML1 Filter Mode Low

Mode of the low registers of filter 1.

0: Low registers are in mask mode

1: Low registers are in identifier list mode

Bit 1 = FMH0 Filter Mode High

Mode of the high registers of filter 0.

0: High registers are in mask mode

1: High registers are in identifier list mode

Bit 0 = FML0 Filter Mode Low

Mode of the low registers of filter 0.

0: Low registers are in mask mode

1: Low registers are in identifier list mode

FILTER x REGISTER[7:0] (CFxR[7:0])

Read / Write

Reset Value: xxxx xxxx (xxh)

In all configurations:

Bit 7:0 = FB[7:0] Filter Bits

Identifier

Each bit of the register specifies the level of the

corresponding bit of the expected identifier.

0: Dominant bit is expected

1: Recessive bit is expected

Mask

Each bit of the register specifies whether the bit of

the associated identifier register must match with

the corresponding bit of the expected identifier or

not.

0: Don’t care, the bit is not used for the comparison

1: Must match, the bit of the incoming identifier

must have the same level has specified in the

corresponding identifier register of the filter.

Note: Each filter x is composed of 8 registers,

CFxR[7:0]. Depending on the scale and mode

configuration of the filter the function of each reg-

ister can differ. For the filter mapping, functions

description and mask registers association, refer

to Section 10.10.5.4Identifier Filtering.

A Mask/Identifier register in mask mode has the

same bit mapping as in identifier list mode.

Note: To modify these registers, the correspond-

ing FACT bit in the CFCR register must be

cleared.

FB7FB6

FB5FB4

FB3FB2

FB1FB0

ST92F124 Datasheet(PDF) 356 Page - STMicroelectronics

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