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ST10F276 Datasheet(PDF) 223 Page - STMicroelectronics |
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ST10F276 Datasheet(HTML) 223 Page - STMicroelectronics |
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223 / 229 page  ST10F276 Electrical characteristics 223/229 Figure 68. SSC master timing 1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received. 1st out bit Last out bit 2nd out bit 2nd in bit 1st in bit SCLK MTSR MRST (1) (2) t308 t307 t308 t307 t305 t305 t306 t305 t304 t303 t300 t301 t302 Last in bit |
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