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MC9S12XEP100J1CAG Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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MC9S12XEP100J1CAG Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
2 / 1036 page ![]() To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the appendices. The following revision history table summarizes changes contained in this document. This document contains information for all constituent modules, with the exception of the S12X CPU. For S12X CPU information please refer to the CPU S12 Reference Manual Version 2 . Revision History Date Revision Level Description Oct, 2006 1.01 VREG, NVM electrical parameter updates Use of external regulator now prohibited Nov, 2006 1.02 Corrected package option code. Added dataflash to derivative table. Included revision history in module sections Removed internal text Dec, 2006 1.03 NVM timing parameters, PLL parameters. Minor typo corrections. Jan, 2007 1.04 NVM timing parameters and EEE description updated. Feb, 2007 1.05 EBI/NVM/IDD parameter updates Partnumber coding explanation updated in Appendix F Ex256 memory map correction Mar, 2007 1.06 ATD/PLL electricals updated Revised FTM section Version ID added to Part ID section May, 2007 1.07 EPROT/FPROT configuration field locations changed !! Various electricals updated following characterization Revised PIM section : corrected ATD pin mapping Revised INT section : software interrupt priorities changed Revised DBG section: NDB functionality, simultaneous arm and disarm Revised SEC section : added disclaimer, corrected backdoor key text Revised SPI section: typo fixes only Revised TIM section : removed redundant table, corrected bit name Revised FTM section: Updated security description. |
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