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93LC86C-I/MS Datasheet(PDF) 16 Page - Microchip Technology |
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93LC86C-I/MS Datasheet(HTML) 16 Page - Microchip Technology |
16 / 38 page 93XX46X/56X/66X/76X/86X DS21929D-page 16 © 2007 Microchip Technology Inc. 3.9 WRITE ALL (WRAL) The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. For 93AAXX and 93LCXX devices, after the last data bit is clocked into DI, the falling edge of CS initiates the self-timed auto-erase and programming cycle. For 93CXX devices, the self-timed auto-erase and pro- gramming cycle is initiated by the rising edge of CLK on the last data bit. Clocking of the CLK pin is not neces- sary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction, but the chip must be in the EWEN status. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL). VCC must be ≥ 4.5V for proper operation of WRAL. FIGURE 3-10: WRAL TIMING FOR 93AAXX AND 93LCXX DEVICES FIGURE 3-11: WRAL TIMING FOR 93CXX DEVICES Note: For devices with PE functionality such as the 93XX76C or 93XX86C, the write sequence requires a logic high signal on the PE pin prior to the rising edge of clock on the last data bit. Note: After the Write All cycle is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. CS CLK DI DO HIGH-Z 1 0 0 01 X ••• x Dx ••• D0 High-Z Busy Ready TWL VCC must be ≥ 4.5V for proper operation of WRAL. TCSL TSV TCZ CS CLK DI DO HIGH-Z 1 0 0 01 X ••• x Dx ••• D0 High-Z Busy Ready TWL TCSL TSV TCZ |
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