PIC18F4685-ISLASHSP datasheet(184/484 Pages) MICROCHIP

184 / 484 page

PIC18F2682/2685/4682/4685

DS39761B-page 182

Preliminary

16.4.6

PROGRAMMABLE DEAD-BAND

DELAY

In half-bridge applications where all power switches are

modulated at the PWM frequency at all times, the power

switches normally require more time to turn off than to

turn on. If both the upper and lower power switches are

switched at the same time (one turned on and the other

turned off), both switches may be on for a short period of

time until one switch completely turns off. During this

brief interval, a very high current (

shoot-through current)

may flow through both power switches, shorting the

bridge supply. To avoid this potentially destructive shoot-

through current from flowing during switching, turning on

either of the power switches is normally delayed to allow

the other switch to completely turn off.

In the Half-Bridge Output mode, a digitally programmable

dead-band delay is available to avoid shoot-through cur-

rent from destroying the bridge power switches. The delay

occurs at the signal transition from the non-active state to

the active state. See Figure 16-4 for illustration. Bits

PDC6:PDC0 of the ECCP1DEL register (Register 16-2)

set the delay period in terms of microcontroller instruction

cycles (TCY or 4 TOSC). These bits are not available on

PIC18F2682/2685 devices, as the standard CCP1

module does not support half-bridge operation.

16.4.7

ENHANCED PWM AUTO-SHUTDOWN

When the ECCP1 is programmed for any of the

Enhanced PWM modes, the active output pins may be

configured

for

auto-shutdown.

Auto-shutdown

immediately places the Enhanced PWM output pins into

a defined shutdown state when a shutdown event occurs.

A shutdown event can be caused by either of the

comparator modules, a low level on the RB0/INT0/

FLT0/AN10 pin, or any combination of these three

sources. The comparators may be used to monitor a

voltage input proportional to a current being monitored in

the bridge circuit. If the voltage exceeds a threshold, the

comparator switches state and triggers a shutdown.

Alternatively, a digital signal on the INT0 pin can also

trigger a shutdown. The auto-shutdown feature can be

disabled by not selecting any auto-shutdown sources.

The auto-shutdown sources to be used are selected

using the ECCPAS2:ECCPAS0 bits (bits<6:4> of the

ECCP1AS register).

When a shutdown occurs, the output pins are

asynchronously placed in their shutdown states, spec-

ified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0

bits (ECCP1AS3:ECCP1AS0). Each pin pair (P1A/P1C

and P1B/P1D) may be set to drive high, drive low or be

tri-stated

(not

driving).

The

ECCPASE

bit

(ECCP1AS<7>) is also set to hold the Enhanced PWM

outputs in their shutdown states.

The ECCPASE bit is set by hardware when a shutdown

event occurs. If automatic restarts are not enabled, the

ECCPASE bit is cleared by firmware when the cause of

the shutdown clears. If automatic restarts are enabled,

the ECCPASE bit is automatically cleared when the

cause of the auto-shutdown has cleared.

If the ECCPASE bit is set when a PWM period begins,

the PWM outputs remain in their shutdown state for that

entire PWM period. When the ECCPASE bit is cleared,

the PWM outputs will return to normal operation at the

beginning of the next PWM period.

Note:

Programmable dead-band delay is not

implemented in PIC18F2682/2685 devices

with standard CCP1 modules.

Note:

Writing to the ECCPASE bit is disabled

while a shutdown condition is active.

ECCP1DEL: PWM DEAD-BAND DELAY REGISTER(1)

R/W-0

PRSEN

PDC6

PDC5

PDC4

PDC3

PDC2

PDC1

PDC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

PRSEN: PWM Restart Enable bit

= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away;

the PWM restarts automatically

= Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM

bit 6-0

PDC6:PDC0: PWM Delay Count bits

Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM

signal to transition to active.

Note 1:

This register is available on PIC18F4682/4685 devices only.

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