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PIC16F685-E/MLQTP Datasheet(PDF) 108 Page - Microchip Technology |
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PIC16F685-E/MLQTP Datasheet(HTML) 108 Page - Microchip Technology |
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108 / 294 page  PIC16F631/677/685/687/689/690 DS41262D-page 106 © 2007 Microchip Technology Inc. TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES REGISTER 8-5: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 U-0 C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: S = Bit is set only R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1VREN: Comparator C1 Voltage Reference Enable bit 1 = CVREF circuit powered on and routed to C1VREF input of Comparator C1 0 = 0.6 Volt constant reference routed to C1VREF input of Comparator C1 bit 6 C2VREN: Comparator C2 Voltage Reference Enable bit 1 = CVREF circuit powered on and routed to C2VREF input of Comparator C2 0 = 0.6 Volt constant reference routed to C2VREF input of Comparator C2 bit 5 VRR: Comparator Voltage Reference CVREF Range Selection bit 1 = Low Range 0 = High Range bit 4 VP6EN: 0.6V Reference Enable bit 1 = Enabled 0 = Disabled bit 3-0 VR<3:0>: Comparator Voltage Reference CVREF Value Selection 0 ≤ VR<3:0> ≤ 15 When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 0000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000 CM2CON1 MC1OUT MC2OUT — — — — T1GSS C2SYNC 00-- --10 00-- --10 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x PIE2 OSFIE C2IE C1IE EEIE — — — — 0000 ---- 0000 ---- PIR2 OSFIF C2IF C1IF EEIF — — — — 0000---- 0000---- PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu REFCON — — BGST VRBB VREN VROE CVROE — --00 000- --00 000- SRCON SR1 SR0 C1SEN C2REN PULSS PULSR — — 0000 00-- 0000 00-- TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator. |
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