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DSPIC30F2012AT20E/ML Datasheet(PDF) 130 Page - Microchip Technology

Part # DSPIC30F2012AT20E/ML
Description  High-Performance, 16-Bit Digital Signal Controllers
PDF  205 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC30F2012AT20E/ML Datasheet(HTML) 130 Page - Microchip Technology

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dsPIC30F2011/2012/3012/3013
DS70139E-page 128
© 2006 Microchip Technology Inc.
Table 17-5 shows the Reset conditions for the RCON
register. Since the control bits within the RCON register
are R/W, the information in the table means that all the
bits are negated prior to the action specified in the
condition column.
TABLE 17-5:
INITIALIZATION CONDITION FOR RCON REGISTER: CASE 1
Table 17-6 shows a second example of the bit
conditions for the RCON register. In this case, it is not
assumed the user has set/cleared specific bits prior to
action specified in the condition column.
TABLE 17-6:
INITIALIZATION CONDITION FOR RCON REGISTER: CASE 2
Condition
Program
Counter
TRAPR IOPUWR EXTR SWR WDTO IDLE
SLEEP POR BOR
Power-on Reset
0x000000
00
0
0
0
0
0
1
1
Brown-out Reset
0x000000
00
0
0
0
0
0
0
1
MCLR Reset during normal
operation
0x000000
00
1
0
0
0
0
0
0
Software Reset during
normal operation
0x000000
00
0
1
0
0
0
0
0
MCLR Reset during Sleep
0x000000
00
1
0
0
0
1
0
0
MCLR Reset during Idle
0x000000
00
1
0
0
1
0
0
0
WDT Time-out Reset
0x000000
00
0
0
1
0
0
0
0
WDT Wake-up
PC + 2
00
0
0
1
0
1
0
0
Interrupt Wake-up from
Sleep
PC + 2(1)
00
0
0
0
0
1
0
0
Clock Failure Trap
0x000004
00
0
0
0
0
0
0
0
Trap Reset
0x000000
10
0
0
0
0
0
0
0
Illegal Operation Trap
0x000000
01
0
0
0
0
0
0
0
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1:
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
Condition
Program
Counter
TRAPR IOPUWR EXTR SWR WDTO IDLE
SLEEP POR BOR
Power-on Reset
0x000000
00
0
0
0
0
0
1
1
Brown-out Reset
0x000000
uu
u
u
u
u
u
0
1
MCLR Reset during normal
operation
0x000000
uu
1
0
0
0
0
u
u
Software Reset during
normal operation
0x000000
uu
0
1
0
0
0
u
u
MCLR Reset during Sleep
0x000000
uu
1
u
0
0
1
u
u
MCLR Reset during Idle
0x000000
uu
1
u
0
1
0
u
u
WDT Time-out Reset
0x000000
uu
0
0
1
0
0
u
u
WDT Wake-up
PC + 2
uu
u
u
1
u
1
u
u
Interrupt Wake-up from
Sleep
PC + 2(1)
uu
u
u
u
u
1
u
u
Clock Failure Trap
0x000004
uu
u
u
u
u
u
u
u
Trap Reset
0x000000
1u
u
u
u
u
u
u
u
Illegal Operation Reset
0x000000
u1
u
u
u
u
u
u
u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1:
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.



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