PIC16F690-ISLASHSSSQTP datasheet(105/294 Pages) MICROCHIP

105 / 294 page

DS41262D-page 103

PIC16F631/677/685/687/689/690

SRCON: SR LATCH CONTROL REGISTER

R/W-0

R/S-0

U-0

SR1(2)

SR0(2)

C1SEN

C2REN

PULSS

PULSR

—

bit 7

bit 0

Legend:

S = Bit is set only

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

SR1: SR Latch Configuration bit(2)

C2OUT pin is the latch Q output

C2OUT pin is the C2 comparator output

bit 6

SR0: SR Latch Configuration bits(2)

C1OUT pin is the latch Q output

C1OUT pin is the Comparator C1 output

bit 5

C1SEN: C1 Set Enable bit

= C1 comparator output sets SR latch

= C1 comparator output has no effect on SR latch

bit 4

C2REN: C2 Reset Enable bit

= C2 comparator output resets SR latch

= C2 comparator output has no effect on SR latch

bit 3

PULSS: Pulse the SET Input of the SR Latch bit

= Triggers pulse generator to set SR latch. Bit is immediately reset by hardware.

= Does not trigger pulse generator

bit 2

PULSR: Pulse the Reset Input of the SR Latch bit

= Triggers pulse generator to reset SR latch. Bit is immediately reset by hardware.

= Does not trigger pulse generator

bit 1-0

Unimplemented: Read as ‘0’

Note 1:

The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on

the pin), regardless of the SR latch operation.

To enable an SR latch output to the pin, the appropriate CxOE and TRIS bits must be properly configured.

PIC16F690-I/SSSQTP Datasheet(PDF) 105 Page - Microchip Technology

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