PIC16F690-ISLASHSSSQTP datasheet(193/294 Pages) MICROCHIP

193 / 294 page

DS41262D-page 191

PIC16F631/677/685/687/689/690

13.13 Master Mode

Master mode of operation is supported in firmware

using interrupt generation on the detection of the Start

and Stop conditions. The Stop (P) and Start (S) bits are

cleared from a Reset or when the SSP module is

disabled. The Stop (P) and Start (S) bits will toggle

based on the Start and Stop conditions. Control of the

I2C bus may be taken when the P bit is set or the bus

is idle and both the S and P bits are clear.

In Master mode, the SCL and SDA lines are

manipulated

clearing

the

corresponding

TRISB<6,4> bit(s). The output level is always low,

irrespective of the value(s) in PORTB<6,4>. So when

transmitting data, a ‘1’ data bit must have the

TRISB<4> bit set (input) and a ‘0’ data bit must have

the TRISB<4> bit cleared (output). The same scenario

is true for the SCL line with the TRISB<6> bit. Pull-up

resistors must be provided externally to the SCL and

SDA pins for proper operation of the I2C module.

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP Interrupt will occur if

enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

Master mode of operation can be done with either the

Slave mode idle (SSPM<3:0> = 1011), or with the

Slave active. When both Master and Slave modes are

enabled, the software needs to differentiate the

source(s) of the interrupt.

13.14 Multi-Master Mode

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions, allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the SSP

module is disabled. The Stop (P) and Start (S) bits will

toggle based on the Start and Stop conditions. Control

of the I2C bus may be taken when bit P (SSPSTAT<4>)

is set, or the bus is idle and both the S and P bits clear.

When the bus is busy, enabling the SSP Interrupt will

generate the interrupt when the Stop condition occurs.

In Multi-Master operation, the SDA line must be

monitored to see if the signal level is the expected

output level. This check only needs to be done when a

high level is output. If a high level is expected and a low

level is present, the device needs to release the SDA

and SCL lines (set TRISB<6,4>). There are two stages

where this arbitration can be lost, these are:

• Address Transfer

• Data Transfer

When the slave logic is enabled, the slave continues to

receive. If arbitration was lost during the address

transfer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be generated.

If arbitration was lost during the data transfer stage, the

device will need to re-transfer the data at a later time.

13.14.1

CLOCK SYNCHRONIZATION AND

THE CKP BIT

When the CKP bit is cleared, the SCL output is forced

to ‘0’; however, setting the CKP bit will not assert the

SCL output low until the SCL output is already sampled

low. Therefore, the CKP bit will not assert the SCL line

until an external I2C master device has already

asserted the SCL line. The SCL output will remain low

until the CKP bit is set and all other devices on the I2C

bus have deasserted SCL. This ensures that a write to

the CKP bit will not violate the minimum high time

requirement for SCL (see Figure 13-12).

PIC16F690-I/SSSQTP Datasheet(PDF) 193 Page - Microchip Technology

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