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ST10F269ZX Datasheet(PDF) 163 Page - STMicroelectronics

Part # ST10F269ZX
Description  16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM
PDF  184 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F269ZX Datasheet(HTML) 163 Page - STMicroelectronics

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ST10F269
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Notes: 1. RW-delay and
t
A refer to the next following bus cycle.
2. Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address
changes before the end of RD have no impact on read cycles.
3. Partially tested, guaranteed by design characterization.
t48
CC
RdCS, WrCS Low Time
(with RW-delay)
21.25 + tC
–
2TCL - 10 + tC
–ns
t49
CC
RdCS, WrCS Low Time
(no RW-delay)
36.875 + tC
–
3TCL - 10 + tC
–ns
t50
CC
Data valid to WrCS
17.25 + tC
–
2TCL - 14 + tC
–ns
t51
SR
Data hold after RdCS
0–
0
–
ns
t53
SR
Data float after RdCS
(with RW-delay) 3
–
21.25 + tF
–
2TCL - 10 + tF
ns
t68
SR
Data float after RdCS
(no RW-delay) 3
–0 + tF
–TCL - 10 + tF
ns
t55
CC
Address hold after
RdCS, WrCS
-10 + tF
–
-10 + tF
–ns
t57
CC
Data hold after WrCS
1.625 + tF
–TCL - 14 + tF
–ns
Symbol
Parameter
Maximum CPU Clock =
32MHz
Variable CPU Clock
1/2 TCL = 1 to 32MHz
Unit
Minimum
Maximum
Minimum
Maximum



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