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TMS320DM6431 Datasheet(PDF) 6 Page - Texas Instruments |
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TMS320DM6431 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 225 page  www.ti.com Revision History TMS320DM6431 Digital Media Processor SPRS342A – NOVEMBER 2006 – REVISED MARCH 2007 This data manual revision history highlights the technical changes made to the SPRS342 device-specific data manual to make it an SPRS342A revision. Scope: Applicable updates to the device family, specifically relating to the device, have been incorporated. • The RSV1 pin (E5, D4) must be left unconnected. Do not connect to power or ground. • Upon exit from the bootloader code, all C64x+ memories are configured as all RAM, Cache is disabled. • This is now a complete document. New sections and subsections have been added. SEE ADDITIONS/MODIFICATIONS/DELETIONS Global Added section cross-references throughout the entire document Section 1.1 Section 1.1, Features: Deleted "/Debug" from the "Fully Software-Compatible With C64x" feature Section 2.1 Section 2.1, Device Characteristics: Table 2-1, Characteristics of the DM6431 Processor: Added "MegaMdodule Rev ID" Updated/Changed the "CPU ID + CPU Rev ID" row to reference the "TMS320DM6437/35/33/31 Digital Media Processor (DMP) [Silicon Revisions 1.1 and 1.0] Silicon Errata (literature number SPRZ250)." Updated/Changed PLL Options "CLKIN1 frequency multiplier (27 MHz reference)" to "MXI/CLKIN frequency multiplier (27 MHz reference)" Section 2.4 Section 2.4, Memory Map Summary: Section 2.4, Memory Map Summary: Added "For all boot modes that default to ..." footnote Table 2-4, Configuration Memory Map Summary: Deleted 0x01BC 0000 — 0x01BC 00FF AET Registers; now "Reserved" Section 2.6 Section 2.6, Terminal Functions: Table 2-5, Boot Terminal Functions: Updated/Changed Bootmode[3:0] Descriptions to reference Section 3.4.1, Boot Modes Updated/Changed EM_BA[1:0]/(AEM0:1) DSECRIPTION from "...pinout type" to ..."pinout mode" Table 2-10, EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001): Updated/Changed the DESCRIPTION for EM_A[12:0] Table 2-11, EMIFA Terminal Functions (EMIFA Pinout Mode 5, AEM[2:0] = 101): Updated/Changed DESPCRIPTION for EM_CS2/GP[12] Table 2-12, DDR2 Memory Controller Terminal Functions: Added "Output" pin direction to the DESCRIPTION for all address bus and control signals Added "bi-directional" to the DESCRIPTION for the DDR2 data bus Table 2-13, EMAC and MDIO Terminal Functions: Updated/Changed the "MTXCLK/GP[73]" DESCRIPTION from "output" to "input" Updated/Changed the "MTXD0/GP[72]" DESCRIPTION from "TXD0" to "MTXD0" Updated/Changed the "MRXD3/GP[82]" DESCRIPTION from "RXD3" to "MRXD3" Added "(I/O/Z)" to the MDIO/GP[83] DESCRIPTION Table 2-14, VPFE Terminal Functions: Updated/Changed the DESCRIPTION for the following signals: CCDC9 through CCDC0 from "CCD AFE mode" to "CCD Raw mode" Added "In 8-bit YCbCr mode, this pin should not be used." to the DESCRIPTION for CCD8 and CCD9 Table 2-23, Standalone GPIO 3.3 V Terminal Functions: Updated/Changed the DESCRIPTION for GP[28] to "... pulled down via an external resistor" Table 2-24, Reserved Terminal Functions: Deleted TYPE for the following signals: RSV4 through RSV15 Section 2.8 Section 2.8, Device and Development-Support Tool Nomenclature: Updated/Changed Figure 2-10, Device Nomenclature Section 5.3 Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted): Updated/Changed CI and CO MAX values from "10 pF" to "5 pF" Updated/Changed the "Measured under the following conditions: ..." footnote 6 Revision History Submit Documentation Feedback |
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