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PS21205 Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor |
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PS21205 Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor |
2 / 8 page MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module> PS21205 TRANSFER-MOLD TYPE INSULATED TYPE Aug. 1999 Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE) Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT Z Drive circuit (15V line) (5V line) (Note 1, 2) VD VNC VNC W AC line input AC line output V U Input signal coditioning Level shifter Drive circuit Protection circuit (UV) Input signal coditioning Input signal coditioning Input signal conditioning Fo logic Protection circuit Protection circuit (UV) Protection circuit (UV) Control supply Under-Voltage protection Drive circuit Drive circuit FO CFO P N1 N Fault output (5V line) (Note 3, 5) High-side input (PWM) (5V line) Note 1,2) Low-side input (PWM) M (Note 6) Bootstrap circuit For detailed description of the boot-strap circuit construction, please contact Mitsubishi Electric DIP-IPM C Z : ZNR (Surge absorber) C : AC filter (Ceramic capacitor 2.2~6.5nF) (Note : Additionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment). C4 C3 C3 : Tight tolerance, temp-compensated electrolytic type C4 : 0.22~2 µF R-category ceramic capacitor for noise filtering. (Note : The capacitance value depends on the PWM control scheme used in the applied system). Note1: To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 7) 2: By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 7) 3: This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1k Ω resistance. (see also Fig. 7) 4: The wiring between the power DC link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22 µF, high voltage type) is recommended to be mounted close to these P and N1 DC power input pins. 5: Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF tFO=1.8ms (Typ.)) 6: High voltage diodes (600V or more) should be used in the bootstrap circuit. H-side IGBTS L-side IGBTS CIN (Note 4) Fig. 3 Inrush current limiter circuit Level shifter Level shifter Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0 µs. 2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible. Drive circuit Drive circuit Protection circuit W V U B C VNC CIN A P N1 N C R Shunt Resistor External protection circuit DIP-IPM L-side IGBTS H-side IGBTS SC Protection Trip Level IC (A) tw ( µs) 2 0 Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault. Collector current waveform |
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