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KSZ9567R Datasheet(PDF) 158 Page - Microchip Technology

Part # KSZ9567R
Description  7-Port Gigabit Ethernet Switch with Audio Video Bridging and Two RGMII/MII/RMII Interfaces
PDF  233 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

KSZ9567R Datasheet(HTML) 158 Page - Microchip Technology

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KSZ9567R
DS00002329E-page 158
 2022 Microchip Technology Inc. and its subsidiaries
5.2.4.2
Port MAC Control 1 Register
5.2.4.3
Port Ingress Rate Limit Control Register
Address:
0xN401
Port N: 1-7
Size:
8 bits
Bits
Description
Type
Default
7
RESERVED
R/W
0b
6
RESERVED
RO
0b
5:4
RESERVED
R/W
00b
3
Back pressure Enable
Back pressure is used only for half duplex. Full duplex uses PAUSE frame
flow control which is enabled separately.
1 = Enable port back pressure
0 = Disable port back pressure
R/W
0b
2:1
RESERVED
R/W
00b
0
Pass All Frames
Bad frames (CRC error, too large, too small) are normally dropped. This
feature allows them to be forwarded for mirroring purposes only.
This bit does not affect filtering of flow control frames. To disable filtering of
flow control frames, refer to the Switch MAC Control 4 Register.
1 = Enable
0 = Disable
R/W
0b
Address:
0xN403
Port N: 1-7
Size:
8 bits
Bits
Description
Type
Default
7
RESERVED
RO
0b
6
Port or Priority Based Ingress Rate Limiting
1 = Ingress rate limiting is port based
0 = Ingress rate limiting is priority based
R/W
0b
5
Ingress PPS Mode
1 = Ingress rate limiting is based on number of packets (PPS mode enabled)
0 = Ingress rate limiting is based on number of bits (PPS mode disabled)
R/W
0b
4
Ingress Rate Limit Flow Control Enable
To use this feature, flow control must also be enabled for this port. Refer to
the XMII Port Control 0 Register for non-PHY ports, and the PHY Auto-
Negotiation Advertisement Register for PHY ports.
1 = Flow control is asserted if the port’s receive rate is exceeded
0 = Flow control is not asserted based on ingress rate limits
R/W
0b



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