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STM32F429NET7TR Datasheet(PDF) 171 Page - STMicroelectronics |
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STM32F429NET7TR Datasheet(HTML) 171 Page - STMicroelectronics |
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171 / 231 page  DocID024030 Rev 6 171/231 STM32F427xx STM32F429xx Electrical characteristics 192 Figure 59. Synchronous multiplexed NOR/PSRAM read timings Table 94. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FMC_CLK period 2THCLK − 1 - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 0 ns td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK -ns td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 ns td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - ns td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0 ns td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) 0 - ns td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - THCLK+0.5 ns td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK − 0.5 - ns td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 0.5 ns td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - ns |
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