L9679P datasheet(181/279 Pages) STMICROELECTRONICS

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DS11627 Rev 7

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L9679P

Watchdog timers

278

Watchdog timers

This device offers a 2-level watchdog control approach. The first control level is given by

means of a temporal watchdog (WD1). The WD1 window times are SPI programmable and

a couple of specific codes have to be written within this window in order to serve the WD1

control. The second control level is featured by an algorithmic seed/key watchdog (WD2).

Unlike the temporal watchdog, the algorithmic watchdog service must be maintained before

a timeout occurs, i.e. there is no restriction on refreshing the watchdog too early. Both WD1

and WD2 watchdog functionalities can be tested through the WD_TEST SPI command.

10.1

Temporal watchdog (WD1)

The temporal watchdog ensures the system software is operating correctly by requiring

periodic service from the microcontroller at a programmable rate. This service (watchdog

refresh) must occur within a time window, and if serviced too early or too late will enter an

error state reported via the FLTSR register (WD1_WDR bit).

The overall WD1 functionality is described in the state diagram reported in Figure 44.

Figure 44. WD1 Temporal watchdog state diagram

Following the description of the WD1 states and signals (most of them reported in the

related SPI registers).

WDT/TM>VWD_OVERRIDE AND

GAPGPS02286

WD1_ERR_CNT++

WD1_LOCKOUT=1

WD1_TOVR=0 /

500ms AND

(from any state) /

WD2_SSMRST OR MCU_SSMRST

WD1_WDR=1

1 ms /

WD1_ERR_TH_WE=1

WD1_ERR_CNT=0

WD1_WDR=0

WD1_LOCKOUT=1

(From any state) /

WSM_Reset

WD1_ERR_CNT++

WD1_LOCKOUT=1

WD1_ERROR /

WD1 RESET

WD1 RUN

WD1 refresh OK /

WD1 TEST

WD1 INITIAL

WD1_LOCKOUT=0

WD1_ERR_TH_WE=0

WD1_WDR=0

WD1 refresh OK /

WD1_LOCKOUT=0

SPI WD1_TEST

OVERRIDE

WD1

SPI WD1_TEST /

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