Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

STM32L443CC Datasheet(PDF) 133 Page - STMicroelectronics

Part # STM32L443CC
Description  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 100DMIPS, 256KB Flash, 64KB SRAM, USB FS, LCD, analog, audio, AES
PDF  215 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L443CC Datasheet(HTML) 133 Page - STMicroelectronics

Back Button STM32L443CC Datasheet HTML 129Page - STMicroelectronics STM32L443CC Datasheet HTML 130Page - STMicroelectronics STM32L443CC Datasheet HTML 131Page - STMicroelectronics STM32L443CC Datasheet HTML 132Page - STMicroelectronics STM32L443CC Datasheet HTML 133Page - STMicroelectronics STM32L443CC Datasheet HTML 134Page - STMicroelectronics STM32L443CC Datasheet HTML 135Page - STMicroelectronics STM32L443CC Datasheet HTML 136Page - STMicroelectronics STM32L443CC Datasheet HTML 137Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 133 / 215 page
background image
DS11421 Rev 4
133/215
STM32L443CC STM32L443RC STM32L443VC
Electrical characteristics
185
6.3.9
PLL characteristics
The parameters given in Table 51 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 21: General operating conditions.
Table 51. PLL, PLLSAI1 characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLL_IN
PLL input clock(2)
-4
-
16
MHz
PLL input clock duty cycle
-
45
-
55
%
fPLL_P_OUT PLL multiplier output clock P
Voltage scaling Range 1
3.0968
-
80
MHz
Voltage scaling Range 2
3.0968
-
26
fPLL_Q_OUT PLL multiplier output clock Q
Voltage scaling Range 1
12
-
80
MHz
Voltage scaling Range 2
12
-
26
fPLL_R_OUT PLL multiplier output clock R
Voltage scaling Range 1
12
-
80
MHz
Voltage scaling Range 2
12
-
26
fVCO_OUT PLL VCO output
Voltage scaling Range 1
96
-
344
MHz
Voltage scaling Range 2
96
-
128
tLOCK
PLL lock time
-
-
15
40
μs
Jitter
RMS cycle-to-cycle jitter
System clock 80 MHz
-40
-
±ps
RMS period jitter
-
30
-
IDD(PLL)
PLL power consumption on
VDD(1)
VCO freq = 96 MHz
-
200
260
μA
VCO freq = 192 MHz
-
300
380
VCO freq = 344 MHz
-
520
650
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the 2 PLLs.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com