IS25LEG-RLLA2:P-TY datasheet(133/193 Pages) ISSI

Part #	IS25LEG-RLLA2:P-TY

Description	SERIAL FLASH MEMORY 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	193 Pages

Scroll/Zoom	100%

Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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IS25LE01GG

IS25WE01GG

Integrated Silicon Solution, Inc.- www.issi.com

133

Rev. A3

10/02/2025

Figure 8.88 FRDDTR Sequence (BDh [EXTADD=1] or BEh, 4-byte address)

CE#

SCK

IO0

IO1

Instruction = BDh/BEh

CE#

SCK

IO0

IO1

4-byte Address

High Impedance

...

Mode 3

Mode 0

30 28 26

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

4 Dummy Cycles

31 29 27

Data Out

...

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

Data Out

24 22 20

25 23 21

7 5

6 4

3 1

2 0

Mode Bits

...

Mode Bits

...

Notes:

1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode

bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

IS25LEG-RLLA2:P-TY Datasheet(PDF) 133 Page - Integrated Silicon Solution, Inc

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