IS25LEG-RMLA2:P-TY datasheet(146/193 Pages) ISSI

Part #	IS25LEG-RMLA2:P-TY

Description	SERIAL FLASH MEMORY 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	193 Pages

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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146 / 193 page

IS25LE01GG

IS25WE01GG

Integrated Silicon Solution, Inc.- www.issi.com

146

Rev. A3

10/02/2025

8.47 READ BANK ADDRESS REGISTER OPERATION (RDBR: 16h/C8h)

The Read Bank Address Register (RDBR) instruction allows the Bank Address Register contents to be read. RDBR

is used to read only a volatile Bank Address Register.

The instruction code is first shifted in. Then the 8-bit Bank Register is shifted out. It is possible to read the Bank

Address Register continuously by providing multiples of eight bits.

Data is shifted in from SI and data is shifted out from SO in SPI sequence whereas data in and out is via four pins

(IO0-IO3) in QPI sequence.

Figure 8.103 Read Bank Address Register Sequence In SPI Mode

Instruction = 16h/C8h

CE #

SCK

Data Out

Mode 3

Mode 0

Figure 8.104 Read Bank Address Register Sequence In QPI Mode

16h/C8h

Mode 3

Mode 0

7:4

3:0

CE#

SCK

IO[3:0]

Data Out

IS25LEG-RMLA2:P-TY Datasheet(PDF) 146 Page - Integrated Silicon Solution, Inc