ADE7566 datasheet(121/136 Pages) AD

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Preliminary Technical Data

ADE7566/ADE7569

Rev. PrA | Page 121 of 136

Table 137. SPI Configuration Register SFR (SPIMOD2, 0xE9)

Bit No.

Mnemonic

Default

Description

Master Mode, SPI Continuous Transfer Mode Enable Bit.

SPICONT

Result

The SPI interface stops after one byte is transferred and SS is deasserted. A new data transfer

can be initiated after a stalled period.

SPICONT

The SPI interface continues to transfer data until no valid data is available in the SPI2CTx SFR.

SS remains asserted until the SPI2CTx SFR and the transmit shift register is empty.

SPI Interface Enable Bit.

SPIEN

Result

The SPI interface is disabled.

SPIEN

The SPI interface is enabled.

SPI Open Drain Output Configuration Bit.

SPIODO

Result

Internal pull-up resistors are connected to the SPI outputs.

SPIODO

The SPI outputs are open-drain and need external pull-up resistors.

SPI Master Mode Enable Bit.

SPIMS_b

Result

The SPI interface is defined as a slave.

SPIMS_b

The SPI interface is defined as a master.

SPI Clock Polarity Configuration Bit (see Figure 97).

SPICPOL

Result

The default state of SCLK is low, and the first SCLK edge is rising. Depending on SPICPHA bit,

the SPI data output changes state on the falling or rising edge of SCLK while the SPI data

input is sampled on the rising or falling edge of SCLK.

SPICPOL

The default state of SCLK is high, and the first SCLK edge is falling. Depending on SPICPHA

bit, the SPI data output changes state on the rising or falling edge of SCLK while the SPI data

input is sampled on the falling or rising edge of SCLK.

SPI Clock Phase Configuration Bit (see Figure 97).

SPICPHA

Result

The SPI data output changes state when SS goes low at the second edge of SCLK and then

every two subsequent edges while the SPI data input is sampled at the first SCLK edge and

then every two subsequent edges.

SPICPHA

The SPI data output changes state at the first edge of SCLK and then every two subsequent

edges while the SPI data input is sampled at the second SCLK edge and then every two

subsequent edges.

Master Mode, LSB First Configuration Bit.

SPILSBF

Result

The MSB of the SPI outputs is transmitted first.

SPILSBF

The LSB of the SPI outputs is transmitted first.

Transfer and Interrupt Mode of the SPI Interface.

TIMODE

Result

Transfer is initiated when data is read from the SPI2CRx SFR, and an interrupt is generated

when there is new data in the SPI2CRx SFR.

TIMODE

Transfer is initiated when data is written to the SPI2CTx SFR, and an interrupt is generated

when the SPI2CTx SFR is empty.

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