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AT91RM9200 Datasheet(PDF) 10 Page - ATMEL Corporation |
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AT91RM9200 Datasheet(HTML) 10 Page - ATMEL Corporation |
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10 / 683 page  10 1768E–ATARM–30-Sep-05 AT91RM9200 3.17 PIO Controller • Up to 32 programmable I/O Lines • Fully programmable through Set/Clear Registers • Multiplexing of two peripheral functions per I/O Line • For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) – Input change interrupt – Glitch filter – Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 3.18 USB Host Port • Compliance with Open HCI Rev 1.0 specification • Compliance with USB V2.0 Full-speed and Low-speed Specification • Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices • Root hub integrated with two downstream USB ports • Two embedded USB transceivers • Supports power management • Operates as a master on the Memory Controller 3.19 USB Device Port • USB V2.0 full-speed compliant, 12 Mbits per second • Embedded USB V2.0 full-speed transceiver • Embedded dual-port RAM for endpoints • Suspend/Resume logic • Ping-pong mode (two memory banks) for isochronous and bulk endpoints • Six general-purpose endpoints – Endpoint 0, Endpoint 3: 8 bytes, no ping-pong mode – Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode – Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode 3.20 Ethernet MAC • Compatibility with IEEE Standard 802.3 • 10 and 100 Mbits per second data throughput capability • Full- and half-duplex operation • MII or RMII interface to the physical layer • Register interface to address, status and control registers • DMA interface, operating as a master on the Memory Controller • Interrupt generation to signal receive and transmit completion • 28-byte transmit and 28-byte receive FIFOs |
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