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AT91RM9200 Datasheet(PDF) 4 Page - ATMEL Corporation |
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AT91RM9200 Datasheet(HTML) 4 Page - ATMEL Corporation |
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4 / 683 page  4 1768E–ATARM–30-Sep-05 AT91RM9200 3. Key Features This section presents the key features of each block. 3.1 ARM920T Processor • ARM9TDMI ™-based on ARM® Architecture v4T • Two instruction sets –ARM® High-performance 32-bit Instruction Set –Thumb ® High Code Density 16-bit Instruction Set • 5-Stage Pipeline Architecture: – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) – Data Memory (M) – Register Write (W) • 16-Kbyte Data Cache, 16-Kbyte Instruction Cache – Virtually-addressed 64-way Associative Cache – 8 words per line – Write-though and write-back operation – Pseudo-random or Round-robin replacement – Low-power CAM RAM implementation • Write Buffer – 16-word Data Buffer – 4-address Address Buffer – Software Control Drain • Standard ARMv4 Memory Management Unit (MMU) – Access permission for sections – Access permission for large pages and small pages can be specified separately for each quarter of the pages – 16 embedded domains – 64 Entry Instruction TLB and 64 Entry Data TLB • 8-, 16-, 32-bit Data Bus for Instructions and Data 3.2 Debug and Test • Integrated Embedded In-Circuit-Emulator • Debug Unit –Two-pin UART – Debug Communication Channel – Chip ID Register • Embedded Trace Macrocell: ETM9 Rev2a – Medium Level Implementation – Half-rate Clock Mode |
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