H838532H datasheet(124/508 Pages) RENESAS

124 / 508 page

Section 5 Power-Down Modes

Rev. 1.00 May 30, 2008 Page 104 of 484

REJ09B0436-0100

Bits 1 and 0: Subactive mode clock select (SA1 and SA0)

These bits select the CPU clock rate (

W/2, φW/4, or φW/8) in subactive mode.

SA1 and SA0 cannot

be modified in subactive mode.

Bit 1

SA1

Bit 0

SA0

Description

W/8

(initial value)

W/4

w/2

* : Don’t care

5.2

Sleep Mode

5.2.1

Transition to Sleep Mode

(1) Transition to Sleep (High-Speed) Mode

The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is

executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON and DTON bits

in SYSCR2 are cleared to 0. In sleep mode CPU operation is halted but the on-chip peripheral

functions. CPU register contents are retained.

(2) Transition to Sleep (Medium-Speed) Mode

The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is

executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2

is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in

sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions are

operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and

MA0 bits in SYSCR1. CPU register contents are retained.

Furthermore, it sometimes acts with half state early timing at the time of transition to sleep

(medium-speed) mode.

H838532H Datasheet(PDF) 124 Page - Renesas Technology Corp