H8SX1663 datasheet(140/1158 Pages) RENESAS

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Section 4 Exception Handling

Rev.1.00 Jun. 07, 2006 Page 88 of 1102

REJ09B0294-0100

Table 4.8

Status of CCR and EXR after Trap Instruction Exception Handling

CCR

EXR

Interrupt Control Mode

I2 to I0



[Legend]

Set to 1

Cleared to 0

:

Retains the previous value.

4.7.2

Sleep Instruction Exception Handling

The sleep instruction exception handling starts when a sleep instruction is executed with the SSBY

bit in SBYCR set to 0 and the SLPIE bit in SBYCR set to 1. The sleep instruction exception

handling can always be executed in the program execution state. In the exception handling, the

CPU operates as follows.

1. The contents of PC, CCR, and EXR are saved in the stack.

2. The interrupt mask bit is updated and the T bit is cleared to 0.

3. An exception handling vector table address corresponding to the vector number specified in

the SLEEP instruction is generated, the start address of the exception service routine is loaded

from the vector table to PC, and program execution starts from that address.

Bus masters other than the CPU may gain the bus mastership after a sleep instruction has been

executed. In such cases the sleep instruction will be started when the transactions of a bus master

other than the CPU has been completed and the CPU has gained the bus mastership.

Table 4.9 shows the state of CCR and EXR after execution of sleep instruction exception

handling.

H8SX1663 Datasheet(PDF) 140 Page - Renesas Technology Corp