H8SX1663 datasheet(168/1158 Pages) RENESAS

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Section 5 Interrupt Controller

Rev.1.00 Jun. 07, 2006 Page 116 of 1102

REJ09B0294-0100

5.6

Interrupt Control Modes and Interrupt Operation

The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt

control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt

control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control

mode 0 and interrupt control mode 2.

Table 5.3

Interrupt Control Modes

Interrupt

Control

Mode

Priority

Setting

Interrupt

Mask Bit

Description

Default

The priority levels of the interrupt sources are fixed

default settings.

The interrupts except for NMI is masked by the I bit.

IPR

I2 to I0

Eight priority levels can be set for interrupt sources

except for NMI with IPR.

8-level interrupt mask control is performed by bits I2 to

I0.

5.6.1

Interrupt Control Mode 0

In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit in CCR of

the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.

1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the

interrupt request is sent to the interrupt controller.

2. If the I bit in CCR is set to 1, NMI is accepted, and other interrupt requests are held pending. If

the I bit is cleared to 0, an interrupt request is accepted.

3. For multiple interrupt requests, the interrupt controller selects the interrupt request with the

highest priority, sends the request to the CPU, and holds other interrupt requests pending.

4. When the CPU accepts the interrupt request, it starts interrupt exception handling after

execution of the current instruction has been completed.

5. The PC and CCR contents are saved to the stack area during the interrupt exception handling.

The PC contents saved on the stack is the address of the first instruction to be executed after

returning from the interrupt handling routine.

6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.

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