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H8SX1663 Datasheet(PDF) 210 Page - Renesas Technology Corp

Part # H8SX1663
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX1663 Datasheet(HTML) 210 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 158 of 1102
REJ09B0294-0100
Bit
Bit Name
Initial
Value
R/W
Description
6
RCDM
0
R/W
RAS Down Mode
Selects the
RAS signal state while a DRAM access is
halted when a basic bus interface area or an on-chip
I/O register is accessed: keep the
RAS signal low (RAS
down mode) and high (
RAS up mode).
This bit is effective when BE = 1. Clearing this bit to 0
with RCDM = 1 in
RAS down mode cancels the RAS
down mode and the
RAS signal goes high.
If the
RAS down mode is selected for the SDRAM
interface, the READ/WRIT command is issued without
issuance of the ACTV command when the same row
address is accessed consecutively.
0: RAS up mode when the DRAM/SDRAM is accessed
1: RAS down mode when the DRAM/SDRAM is
accessed
5
DDS
0
R/W
DMAC Single Address Transfer Option
Selects whether a DMAC single address transfer
through the DRAM/SDRAM interface is enabled only in
full access mode or is also enabled in fast-page access
mode.
When clearing the BE bit to 0 to disable a burst access
to the DRAM/SDRAM interface, a DMAC single address
transfer is performed in full access mode regardless of
this bit.
This bit does not affect an external access by other bus
masters or a DMAC dual address transfer. Setting this
bit to 1 changes the
DACK output timing.
0: DMAC single address transfer through the
DRAM/SDRAM is enabled only in full access mode
1: DMAC single address transfer through the
DRAM/SDRAM is also enabled in fast-page access
mode



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