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H8SX1663 Datasheet(PDF) 218 Page - Renesas Technology Corp

Part # H8SX1663
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX1663 Datasheet(HTML) 218 Page - Renesas Technology Corp

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Section 6 Bus Controller (BSC)
Rev.1.00 Jun. 07, 2006 Page 166 of 1102
REJ09B0294-0100
Bit
Bit Name
Initial
Value
R/W
Description
3
SLFRF
0
R/W
Self-Refresh Enable
Selects the self-refresh mode for the DRAM/SDRAM
interface when a transition to the software standby
mode is made with this bit set to 1. To perform a refresh
cycle by setting the RFSHE bit is set to 1, this bit is
effective.
To perform a self-refresh cycle when the SDRAM
interface is selected, enable the CKE output by setting
the OEE bit in DRAMCR.
0: Disables self-refresh
1: Enables self-refresh
2
1
0
TPS2
TPS1
TPS0
0
0
0
R/W
R/W
R/W
Precharge Cycle Control during Self-Refresh
Selects the number of precharge cycles immediately
after a self-refresh cycle. The number of actual number
of precharge cycles is the sum of the numbers indicated
by these bits and bits TPC1 and TPC0.
000: No wait cycle inserted
001: One wait cycle inserted
010: Two wait cycles inserted
010: Three wait cycles inserted
010: Four wait cycles inserted
010: Five wait cycles inserted
010: Six wait cycles inserted
010: Seven wait cycles inserted
Note: Only 0 can be written to this bit, to clear the flag.



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