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H8SX1663 Datasheet(PDF) 223 Page - Renesas Technology Corp |
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H8SX1663 Datasheet(HTML) 223 Page - Renesas Technology Corp |
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223 / 1158 page ![]() Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 171 of 1102 REJ09B0294-0100 Divided clock synchronization cycle T 1 Address I φ B φ AS CSn RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 Read LHWR LLWR Write T 2 T sy BS RD/ WR Figure 6.6 System Clock: External Bus Clock = 4:1, External 2-State Access |
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