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H8SX1663 Datasheet(PDF) 245 Page - Renesas Technology Corp |
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H8SX1663 Datasheet(HTML) 245 Page - Renesas Technology Corp |
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245 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 193 of 1102 REJ09B0294-0100 6.6.3 Basic Timing This section describes the basic timing when the data is specified as big endian. (1) 16-Bit 2-State Access Space Figures 6.15 to 6.17 show the bus timing of 16-bit 2-state access space. When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even addresses access, and the lower byte data bus (D7 to D0) is used for odd addresses. No wait cycles can be inserted. 1. n = 0 to 7 2. When RDNn = 0 3. When DKC = 0 Valid Invalid Valid T 1 T 2 Address CSn AS RD D15 to D8 D7 to D0 D15 to D8 D7 to D0 LHWR LLWR Read Write Notes: High level High-Z B φ Bus cycle BS RD/ WR DACK Figure 6.15 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address) |
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