M32CSLASH86 datasheet(386/505 Pages) RENESAS

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Page 363

23. CAN Module

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23.4.2.1 When the INTSEL Bit is Set to "0"

If the CAN-associated interrupt is generated by one of the interrupt request source listed in 23.4.2

CANij Interrupts, the corresponding bit in the CiSISTR register (i=0,1) is set to "1" (interrupt re-

quested) when the CANi slot k completes a transmission or a reception. The corresponding bit in the

CiEISTR register is set to "1" (interrupt requested) when the CANi module detects a bus error, moves

into an error-passive state, or moves into a bus-off state.

The CANi interrupt request signal is set to "1" when the corresponding bit in the CiSISTR or CiEISTR

is set to "1" and the corresponding bit in the CiSIMKR or CiEIMKR is set to "1"

When the CAN0 interrupt request signal changes "0" to "1", all CAN0jR bits (j=0 to 2) in the IIO9IR to

IIO11IR registers are set to "1" (interrupt requested).

If at least one of the CAN0jE bits in the IIO9IE to IIO11IE registers is set to "1" (interrupt enabled), the

IR bits in the corresponding CAN0IC to CAN2IC registers are set to "1" (interrupt requested). The

CAN0 interrupt request signal remains set to "1" if another interrupt request source causes a corre-

sponding bit in the C0SISTR or C0EISTR to be set to "1" and the corresponding bit in the C0SIMKR or

C0EIMKR to be set to "1" after the CAN0 interrupt request signal changes "0" to "1". The CAN0jR and

IR bits also remain unchanged.

When the CAN1 interrupt request signal changes "0" to "1", all three CAN1jR bits in the IIO0IR to

IIO1IR and IIO5IR registers are set to "1" (interrupt requested).

If at least one of the CAN1jE bits in the IIO0IE to IIO1IE and IIO5IE registers is set to "1", the IR bits in

the corresponding CAN3IC to CAN5IC registers are set to "1". The CAN0 interrupt request signal

remains set to "1" if another interrupt request causes the corresponding bit in the C1SISTR or

C1EISTR to be set to "1" and the corresponding bit in the C1SIMKR or C1EIMKR to be set to "1" after

the CAN1 interrupt request signal changes "0" to "1". The CAN1jR and IR bits also remain unchanged.

Bits in the CiSISTR or CiEISTR register and CANijR bits (i=0,1, j=0 to 2) in the IIO0IR to IIO1IR, IIO5IR

or IIO9IR to IIO11IR registers are not set to "0" automatically, interrupt acknowledgment notwithstand-

ing. Set these bits to "0" by program.

The CANi interrupts are acknowledged when the CANijR bit in the IIO0IR to IIO1IR, IIO5IR or IIO9IR to

IIO11IR register and the corresponding bit in the CiSISTR or CiEISTR register are set to "0". If these

bits remain set to "1", all CAN-associated interrupt request source become invalid.

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