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HD6433635SW Datasheet(PDF) 189 Page - Renesas Technology Corp |
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HD6433635SW Datasheet(HTML) 189 Page - Renesas Technology Corp |
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189 / 418 page  175 Bit 2—Compare Match Flag L (CMFL): Bit 2 is a status flag indicating a compare match between TCFL and OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2: CMFL Description 0 [Clearing conditions] (initial value) After reading CMFL = 1, cleared by writing 0 to CMFL 1 [Setting conditions] Set when the TCFL value matches the OCRFL value Bit 1—Timer Overflow Interrupt Enable L (OVIEL): Bit 1 enables or disables TCFL overflow interrupts. Bit 1: OVIEL Description 0 TCFL overflow interrupt disabled (initial value) 1 TCFL overflow interrupt enabled Bit 0—Counter Clear L (CCLRL): Bit 0 selects whether or not TCFL is cleared when a compare match occurs between TCFL and OCRFL. Bit 0: CCLRL Description 0 TCFL clearing by compare match disabled (initial value) 1 TCFL clearing by compare match enabled |
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