HD6433635SW datasheet(246/418 Pages) RENESAS

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232

Serial Status Register (SSR)

Bit

76543210

TDRE

RDRF

OER

FER

PER

TEND

MPBR

MPBT

Initial value

10000100

Read/Write

R/(W)*

R/W

Note: * Only a write of 0 for flag clearing is possible.

The serial status register (SSR) is an 8-bit register containing status flags for indicating SCI3

states, and containing the multiprocessor bits.

SSR can be read and written by the CPU at any time, but the CPU cannot write a 1 to the status

flags TDRE, RDRF, OER, PER, and FER. To clear these flags to 0 it is first necessary to read a 1.

Bit 2 (TEND) and bit 1 (MPBR) are read-only bits and cannot be modified.

SSR is initialized to H'84 upon reset or in standby mode, watch mode, subactive mode, or

subsleep mode.

Bit 7—Transmit Data Register Empty (TDRE): Bit 7 is a status flag indicating that data has

been transferred from TDR to TSR.

Bit 7: TDRE

Description

Indicates that transmit data written to TDR has not been transferred to TSR

[Clearing conditions]

• After reading TDRE = 1, cleared by writing 0 to TDRE.

• When data is written to TDR by an instruction.

Indicates that no transmit data has been written to TDR, or the transmit data

written to TDR has been transferred to TSR

(initial value)

[Setting conditions]

• When bit TE in SCR3 is cleared to 0.

• When data is transferred from TDR to TSR.

HD6433635SW Datasheet(PDF) 246 Page - Renesas Technology Corp