M16CSLASH26 datasheet(197/239 Pages) RENESAS

197 / 239 page

CPU Rewrite Mode (Flash Memory Version)

191

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Flash memory control register 1 (FMR1):

Bit 1 allows the user to enter EW1 mode. This bit is relevant only if bit FMR01 is set.

Bit 7, when set to "0", inserts one wait state per access to Block A or B - regardless of the value of

PM17. Wait state insertion during access to all other blocks, as well as to internal RAM, is controlled

by PM17 - regardless of the setting of FMR17. In cases where E/W cycles to Block A or B exceed 100

times (D7, D9, U7, U9), please set FMR17 to "1" (with wait).

Flash memory control register 4 (FMR4):

Bit 0 must be set to enable the erase-suspend feature.

Bit 1 is to be used to request a suspend of an erase operation. This bit is set automatically in EW1 by

a maskable interrupt, and by software in EW0. This bit is to be always cleared by software at the end

of the erase suspend.

Bit 6 indicates suspend status. Poll this bit in EW0 after requesting a suspend, before accessing the

flash.

M16C/26 Datasheet(PDF) 197 Page - Renesas Technology Corp