M38049FFHKP datasheet(120/387 Pages) RENESAS

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1-102

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

HARDWARE

FUNCTIONAL DESCRIPTION SUPPLEMENT

Timing After Interrupt

The interrupt processing routine begins with the machine cycle fol-

lowing the completion of the instruction that is currently in

execution.

Figure 93 shows a timing chart after an interrupt occurs, and Fig-

ure 94 shows the time up to execution of the interrupt processing

routine.

Fig. 93 Timing chart after an interrupt occurs

Fig. 94 Time up to execution of the interrupt processing routine

PCH

PCL

S, SPS

S-2, SPS

S-1, SPS

AL, AH

: CPU operation code fetch cycle

(This is an internal signal that cannot be observed from the external unit.)

: Vector address of each interrupt

: Jump destination address of each interrupt

: “0016” or “0116”

SYNC

BL, BH

AL, AH

SPS

Data bus

Not used

Address bus

SYNC

Interrupt request generated

Main routine

Interrupt processing routine

7 to 23 cycles

(When f(XIN) = 8.4 MHz, 0.83

µs to 2.74 µs)

2 cycles

5 cycles

Start of interrupt processing

0 to 16 cycles

Waiting time for

post-processing

of pipeline

Stack push and

Vector fetch

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