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LTC4357IDCB-TRPBF Datasheet(PDF) 8 Page - Linear Technology |
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LTC4357IDCB-TRPBF Datasheet(HTML) 8 Page - Linear Technology |
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8 / 12 page  LTC4357 8 4357fb VDD Hold-Up Circuit In the event of an input short, parasitic inductance between the input supply of the LTC4357 and the load bypass capacitor may cause VDD to glitch below its minimum operating voltage. This causes the turn-off time (tOFF) to increase. To preserve the fast turn-off time, local output bypassing of 39μF is sufficient at voltages less than 30V. At higher voltages, 100μF is adequate. As an alternative to local bypassing, a 100 Ω, 0.1μF RC hold-up circuit on the VDD pin can be used, shown in Figure 2. In applications with unusually large inductance or load current greater than 10A, use 100 Ω and 1μF. Design Example The following design example demonstrates the calcula- tions involved for selecting components in a 12V system with 10A maximum load current (see Figure 3). Figure 3. 12V, 10A Diode-OR APPLICATIONS INFORMATION First, calculate the RDS(ON) of the MOSFET to achieve the desired forward drop at full load. Assuming VDROP = 0.1V, RDS(ON) VDROP I LOAD = 0.1V 10A RDS(ON) 10m The Si4874DY offers a good solution, in an S8 package with RDS(ON) = 10mΩ(max) and BVDSS of 30V. The maximum power dissipation in the MOSFET is: P = ILOAD2 • RDS(ON) = (10A)2 • 10mΩ = 1W With less than 39μF of local bypass, the recommended RC values of 100 Ω and 0.1μF were used in Figure 3. Since BVDSS + VIN is much less than 100V, output clamp- ing is unnecessary. Figure 2. Two Methods of Protecting Against Collapse of VDD From Input Short and Stray Inductance 4357 F02 LTC4357 GND IN OUT VDD GATE Si4874DY VIN 12V R1 100Ω C1 0.1μF LTC4357 GND IN OUT VDD GATE Si4874DY VIN 12V CBYPASS 39μF 4357 F03 LTC4357 GND IN OUT VDD GATE Si4874DY VIN1 12V VOUT TO LOAD LTC4357 GND IN OUT VDD GATE Si4874DY VIN2 12V 100Ω 100Ω 0.1μF 0.1μF |
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