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SM59R16A2 Datasheet(PDF) 55 Page - SyncMOS Technologies,Inc |
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SM59R16A2 Datasheet(HTML) 55 Page - SyncMOS Technologies,Inc |
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55 / 67 page  SM59R16A2/SM59R08A2 8-Bit Micro-controller 64KB/32KB ISP Flash & 2KB RAM embedded Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 55 Ver.B SM59R16A2/SM59R08A2 06/2009 Mnemonic: SPIS Address: F5h 7 6 5 4 3 2 1 0 Reset - SPIMLS SPIOV SPITXIF SPITDR SPIRXIF SPIRDR SPIRS 40h SPIMLS: MSB or LSB output /input first “1” : MSB output/input first “0” : LSB output/input first SPIOV: Overflow flag. When SPIRDR is set (one byte in SPIRXD but has not been taken away) and the next data also enters (there is no blocking function), this flag will be set to inform that the received data in SPIRXD is damaged by this overflow. It is clear by hardware when SPIRDR is cleared. SPITXIF: Transmit Interrupt Flag. This bit is set when the data of the SPITXD register is downloaded to the shift register. SPITDR: Transmit Data Ready. When MCU finish writing data to SPITXD register, the MCU needs to set this bit to ‘1’ to inform the SPI module to send the data. After SPI module finishes sending the data from SPITXD or SPITXD is downloaded to shift register, this bit will be cleared automatically. SPIRXIF: Receive Interrupt Flag. This bit is set after the SPIRXD is loaded with a newly receive data. SPIRDR: Receive Data Ready. When a byte is received, SPIRDR is set as a flag to inform MCU. The MCU must clear this bit after it gets the data from SPIRXD register. If the SPI module on the transmit side writes new data into the SPIRXD before this bit is cleared, then the data will be overwritten. SPIRS: Receive Start. This bit set to “1” to inform the SPI module to receive the data into SPIRXD register. Mnemonic: SPITXD Address: F3h 7 6 5 4 3 2 1 0 Reset SPITXD[7:0] 00h SPITXD[7:0]: Transmit data buffer. Mnemonic: SPIRXD Address: F4h 7 6 5 4 3 2 1 0 Reset SPIRXD[7:0] 00h SPIRXD[7:0]: Receive data buffer. |
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